1. Field of the Invention
The present invention relates to a stacked multi-chip package in which a plurality of chips are encapsulated in a stacked state, and to a process for fabricating a chip structuring the multi-chip package and to a wire-bonding process.
2. Description of the Related Art
In recent years, while increases in capability, function as well as the miniaturization of of electronic devices have been remarkable, further progress in raising the capabilities of mounted semiconductor devices and high-density packaging have been called for. Accordingly, the demand for stacked multi-chip packages, in which semiconductor devices are implemented three-dimensionally, for thin-form, high volume devices such as I.C. memory cards has become very considerable.
FIG. 12 shows a conventional stacked multi-chip package 100 in which semiconductor devices are mounted in three dimensions. The stacked multi-chip package 100 is structured by chips 102 and 104, a glass epoxy substrate 106, and solder balls 105. Chips 102 and 104 are formed at substantially the same size. Chips 102 and 104 are mounted on the glass epoxy substrate 106, and the solder balls 105 are provided at a lower face side of the glass epoxy substrate 106. Thus, the stacked multi-chip package 100 is a two-chip layer structure in which the chips 102 and 104 are stacked.
Hereinafter, the chip 102 is referred to as the upper chip 102 and the chip 104 is referred to as the lower chip 104. The upper chip 102 and the lower chip 104 are electrically connected, via gold wires (Au wires) 110, by a wire-bonding process with bonding posts 108 which are provided on the glass epoxy substrate 106.
Here, because the upper chip 102 and the lower chip 104 are formed so that they are substantially the same size, a spacer 112 is disposed between the upper chip 102 and the lower chip 104, and a gap is formed between the upper chip 102 and the lower chip 104 by the spacer 112. Thus, at least one connection between the lower chip 104 and the bonding posts 108 by one or more Au wires 110 is enabled.
However, in the stacked multi-chip package 100 having the structure described above, only the Au wires 110 are connected between the upper chip 102 and the lower chip 104, and the gap between the upper chip 102 and the lower chip 104 is not utilized effectively. Moreover, even though there are only two chips, the stacked multi-chip package 100 has substantially the same height as a three chip layer structure, and the resulting thickness of the stacked multi-chip package 100 is large. Consequently, the stacked multi-chip package 100 cannot be mounted in electronic devices of a standard size, generally where the maximum thickness is 1.4 mm, or a thin-form size, generally where the maximum thickness is 1.2 mm.